THRESHOLD VOLTAGE MODELING AND THE SUBTHRESHOLD REGIME OF OPERATION OF SHORT-CHANNEL MOSFETS

We present a new analytical model for the subthreshold regime of operation of short-channel MOSFET's and develop expressions for the threshold-voltage shift associated with the Drain-Induced Barrier Lowering (DIBL) caused by the application of a drain bias. The model is based on the concept of charge sharing, where the depletion charge under the gate is identified with counter charges on the gate electrode and in the source and drain contacts. In particular, we estimate the amount of drain-bias-induced depletion charge in the channel and develop an expression for the distribution of this charge along the channel based on a simplified two-dimensional solution of Poisson's equation. From this distribution, it is possible to find the lowering of the potential barrier between the source and the channel, and the corresponding threshold-voltage shift. The results are compared with experimental data for deep-submicrometer NMOS devices. Expressions for the subthreshold current and for a generalized Unified Charge Control Model (UCCM) for short-channel MOSFET's are presented. We expect that our theory is applicable to deep-submicrometer devices (with gate length larger than 0.1 mum). The model is suitable for implementation in circuit simulators.