MASTERSLICE LSI FOR SUB-NANOSECOND RANDOM LOGIC

被引：4

作者：

BRAECKELMANN, W

WILHELM, W

GRAUL, J

KAISER, H

机构：

[1] Siemens AG, Munich, Germany

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1979年 / 14卷 / 05期

关键词：

D O I：

10.1109/JSSC.1979.1051279

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the design and implementation of subnanosecond gate arrays with a complexity up to 700 gates. There are three different basic arrays with either 24 or 36 cells or 24 cells plus a 128 bit RAM. Each cell has the logic power of a small MSI. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

引用

页码：829 / 832

页数：4