ELECTRICAL CHARACTERISTICS OF TEXTURED POLYSILICON OXIDE PREPARED BY A LOW-TEMPERATURE WAFER LOADING AND N-2 PREANNEALING PROCESS

被引：20

作者：

WU, SL ^{[1
]}

LIN, TY ^{[1
]}

LEE, CL ^{[1
]}

LEI, TF ^{[1
]}

机构：

[1] NATL CHIAO TUNG UNIV,INST ELECTR,HSINCHU,TAIWAN

来源：

IEEE ELECTRON DEVICE LETTERS | 1993年 / 14卷 / 03期

关键词：

D O I：

10.1109/55.215128

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-temperature wafer loading and N2 preannealing process is used to grow a thin textured polysilicon oxide. The polyoxide grown on the heavily doped polysilicon film exhibits less oxide tunneling leakage current and higher dielectric strength when the top electrode is positively biased.

引用

页码：113 / 114

页数：2

共 4 条

[1] EVIDENCE FOR SURFACE ASPERITY MECHANISM OF CONDUCTIVITY IN OXIDE GROWN ON POLYCRYSTALLINE SILICON [J].

ANDERSON, RM ;

KERR, DR .

JOURNAL OF APPLIED PHYSICS, 1977, 48 (11) :4834-4836

[2] THERMAL SIO2-FILMS ON N+ POLYCRYSTALLINE SILICON - ELECTRICAL-CONDUCTION AND BREAKDOWN [J].

FARAONE, L .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1986, 33 (11) :1785-1794

[3]

Ono T., 1985, International Electron Devices Meeting. Technical Digest (Cat. No. 85CH2252-5), P380

[4]

WU SL, 1992, J APPL PHYS, V68, P1378

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