SCHEDULING SYNCHRONOUS DATA-FLOW GRAPHS FOR EFFICIENT LOOPING

被引:16
作者
BHATTACHARYYA, SS [1 ]
LEE, EA [1 ]
机构
[1] UNIV CALIF BERKELEY,DEPT EECS,BERKELEY,CA 94720
来源
JOURNAL OF VLSI SIGNAL PROCESSING | 1993年 / 6卷 / 03期
关键词
D O I
10.1007/BF01608539
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Synchronous dataflow (SDF) has been used to synthesize code for programmable DSPs to implement multirate and block oriented signal processing systems. However, with large block sizes, or significant sample rate changes, program memory consumption becomes a critical problem. This article develops a compile-time algorithm for scheduling SDF graphs to exploit opportunities for looping-the successive reoccurrence of identical firing patterns. Because SDF graphs allow actors to produce or consume an arbitrary number of tokens on each input or output, complicated control flow may result. Yet in static scheduling, it is desirable to execute sections of the target code within loop constructs, such as ''do-while,'' to reduce program-memory requirements. To do this, the SDF graph is hierarchically clustered, carefully avoiding deadlock while exposing looping opportunities. Results of applying these loop-extraction algorithms show orders of magnitude of compaction for target program code space on programmable DSPs compared to in-line code.
引用
收藏
页码:271 / 288
页数:18
相关论文
共 13 条
[1]  
BHATTACHARYYA SS, 1992, UCBERL M9230 UC BERK
[2]  
DENNIS JB, MITLCSTM61
[3]  
HA S, 1991, JUN EUR SIM C
[4]  
HILFINGER PN, 1989, SILAGE REFERENCES MA
[5]  
HO WH, 1988, VLSI SIGNAL PROCESSI, V3
[6]  
HO WH, 1988, CODE GENERATION DIGI
[7]  
HOW S, 1990, CODE GENERATION MULT
[8]  
Lee E. A., 1989, IEEE ASSP Magazine, V6, P4, DOI 10.1109/53.16934
[9]   Programmable DSP architectures. - Part 1 [J].
Lee, Edward A. .
IEEE ASSP magazine, 1988, 5 (04) :4-19
[10]   STATIC SCHEDULING OF SYNCHRONOUS DATA FLOW PROGRAMS FOR DIGITAL SIGNAL-PROCESSING [J].
LEE, EA ;
MESSERSCHMITT, DG .
IEEE TRANSACTIONS ON COMPUTERS, 1987, 36 (01) :24-35