HIGH-PERFORMANCE DEVICES FOR A 0.15-MU-M CMOS TECHNOLOGY

Devices have been designed and fabricated for a CMOS technology with the nominal channel length of 0.15 mum and minimum channel length below 0.1 mum. In order to minimize short-channel effects (SCE's) down to channel lengths below 0.1 mum, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF2 implant) were used. Maximum high V(DS) threshold rolloff was 250 mV at effective channel length of 0.06 mum. For the minimum channel length of 0.1 mum, the loaded (FI = FO = 3, C(L) = 240 fF) and unloaded delays were 150 and 25 ps, respectively.