A TESTABLE CMOS ASYNCHRONOUS COUNTER

A testable design for an asynchronous n-bit CMOS counter is presented, with test inputs that provide full coverage for stuck-at and stuck-open faults. Test time is shown to be O(n), where the counter outputs are not observable, compared to O(n2) time for a synchronous counter. There are three control signals required for the testable counter as opposed to one reset signal for the base counter. The testable counter incorporates a scan path, utilizing the state storage in the counter cells, whereby the counter is converted into an n-bit “master-slave” asynchronous shift register with the counter’s request input also being used as the shift-register input. The only observable outputs are the acknowledge and carry-out signals. The counter utilizes two-cycle (transition) signaling and guarantees that new output values are available before acknowledge is toggled. Two 16-b counters, one base design and one scan-based design, have been fabricated on the same chip (2.0-µm n-well CMOS) through MOSIS. Four parts were received, all of which passed the test suites developed. Speed testing of the parts shows a count rate of 22.2 MHz for the base design counter versus 21.0 MHz for the scan design, indicating a speed degradation of 5.8% for the testable design as compared to the base design. The testable design is achieved with a 15% increase in transistor count (from 52 to 60 per bit), and a corresponding increase in chip area of approximately 6%. © 1990 IEEE