HIGH-QUALITY SIO2/SI INTERFACES OF POLYCRYSTALLINE SILICON THIN-FILM TRANSISTORS BY ANNEALING IN WET ATMOSPHERE

被引：53

作者：

SANO, N ^{[1
]}

SEKIYA, M ^{[1
]}

HARA, M ^{[1
]}

KOHNO, A ^{[1
]}

SAMESHIMA, T ^{[1
]}

机构：

[1] KYUSHU UNIV,FAC SCI,FUKUOKA 812,JAPAN

来源：

IEEE ELECTRON DEVICE LETTERS | 1995年 / 16卷 / 05期

关键词：

D O I：

10.1109/55.382225

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO2 films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO2 and crystalline Si was investigated by capacitance-voltage (C-V) measurements, An H2O vapor annealing at 270 degrees C for 30 min efficiently decreased the interface trap density to 2.0 x 10(10) cm(-2) eV(-1), and the effective oxide charge density from 1 x 10(12) to 5 x 10(9) cm(-2). This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270 degrees C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm(2) V-1 s(-1) and the threshold voltage decreased from -5.5 to -1.7 V.

引用

页码：157 / 160

页数：4

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