TRAM - A DESIGN METHODOLOGY FOR HIGH-PERFORMANCE, EASILY TESTABLE, MULTIMEGABIT RAMS

被引：7

作者：

JARWALA, NT ^{[1
]}

PRADHAN, DK ^{[1
]}

机构：

[1] AT&T BELL LABS,PRINCETON,NJ 08540

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1988年 / 37卷 / 10期

基金：

美国国家科学基金会;

关键词：

MEMORY SELF-TESTING - MULTIMEGABIT DYNAMIC RAM - TRAM ARCHITECTURE - TREE RANDOM ACCESS MEMORY (TRAM);

D O I：

10.1109/12.5985

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：1235 / 1250

页数：16

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