2-CHANNEL 5 GBIT/S SILICON BIPOLAR MONOLITHIC RECEIVER FOR PARALLEL OPTICAL INTERCONNECTS

被引：24

作者：

WIELAND, J ^{[1
]}

DURAN, H ^{[1
]}

FELDER, A ^{[1
]}

机构：

[1] SIEMENS AG,CORP RES & DEV,D-81730 MUNICH,GERMANY

来源：

ELECTRONICS LETTERS | 1994年 / 30卷 / 04期

关键词：

INTEGRATED CIRCUITS; OPTICAL RECEIVERS;

D O I：

10.1049/el:19940246

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A two-channel optical receiver array is monolithically integrated in a pre-production 0.8 mum silicon bipolar technology. Each channel converts incident light into a differential digital signal, operates up to 5Gbit/s, consumes 30 mW and fits into a chip area of 50 x 240 mum2.

引用

页码：358 / 359

页数：2

共 9 条

[1]

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[2]

LANG H, 1991, SEP ECOC 91 PAR

[3]

LI CS, 1993, FEB OFC IOOC 93 SAN

[4]

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[5]

POPP J, 1990, SEP ESSDERC 90 NOTT, P571

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REIN, HM ;

BERTAGNOLLI, E ;

FELDER, A ;

SCHMIDT, L .

ELECTRONICS LETTERS, 1992, 28 (14) :1295-1296

[7]

TAKAI A, 1993, SEP ECOC 93 MONTR

[8]

TREITINGER L, 1993, SEP ECOC 93 MONTR

[9] OPTICAL RECEIVER ARRAY IN SILICON BIPOLAR TECHNOLOGY WITH SELFALIGNED, LOW PARASITIC III/V DETECTORS FOR DC-1 GBIT/S PARALLEL LINKS [J].

WIELAND, J ;

MELCHIOR, H ;

KEARLEY, MQ ;

MORRIS, CR ;

MOSELEY, AM ;

GOODWIN, MJ ;

GOODFELLOW, RC .

ELECTRONICS LETTERS, 1991, 27 (24) :2211-2213

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