We report on the generation of a discrete trap state during negative gate bias stress in pentacene single-crystal "flip-crystal" field-effect transistors with a SiO2 gate dielectric. Trap densities of up to 2 center dot 10(12) cm(-2) were created in the experiments. Trap formation and trap relaxation are distinctly different above and below similar to 280 K. In devices in which a self-assembled monolayer on top of the SiO2 provides a hydrophobic insulator surface we do not observe trap formation. These results indicate the microscopic cause of the trap state to be related to molecular layers of water adsorbed on the SiO2 surface.
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Univ Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, NetherlandsUniv Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, Netherlands
Jurchescu, OD
Baas, J
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Univ Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, NetherlandsUniv Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, Netherlands
Baas, J
Palstra, TTM
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Univ Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, NetherlandsUniv Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, Netherlands
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Univ Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, NetherlandsUniv Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, Netherlands
Jurchescu, OD
Baas, J
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机构:
Univ Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, NetherlandsUniv Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, Netherlands
Baas, J
Palstra, TTM
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h-index: 0
机构:
Univ Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, NetherlandsUniv Groningen, Solid State Chem Lab, Ctr Mat Sci, NL-9747 AG Groningen, Netherlands