A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation

被引：30

作者：

Falakshahi, K ^{[1
]}

Yang, CKK ^{[1
]}

Wooley, BA ^{[1
]}

机构：

[1] Stanford Univ, Ctr Integrated Syst, Stanford, CA 94305 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 05期

关键词：

current calibration; digital-to-analog conversion; mixed analog-digital integrated circuits; multibit modulators; pipelined adders; sigma-delta modulation;

D O I：

10.1109/4.760370

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 14-bit digital-to-analog converter based on a fourth-order multibit sigma-delta modulator is described. The digital modulator is pipelined to minimize both its power dissipation and design complexity. The 6-bit output of this modulator is converted to analog using 64 current-steering cells that are continuously calibrated to a reference current. This converter achieves 85-dB dynamic range at 5-MHz signal bandwidth, with an oversampling ratio of 12, The chip was fabricated in a 0.5-mu m CMOS technology and operates from a single 2.5-V supply.

引用

页码：607 / 615

页数：9