Mobility enhancement of high-k gate stacks through reduced transient charging

被引:32
作者
Kirsch, PD [1 ]
Sim, JH [1 ]
Song, SC [1 ]
Krishnan, S [1 ]
Peterson, J [1 ]
Li, HJ [1 ]
Quevedo-Lopez, M [1 ]
Young, CD [1 ]
Choi, R [1 ]
Moumen, N [1 ]
Majhi, P [1 ]
Wang, Q [1 ]
Ekerdt, JG [1 ]
Bersuker, G [1 ]
Lee, BH [1 ]
机构
[1] SEMATECH, Austin, TX 78741 USA
来源
PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2005年
关键词
GROWTH;
D O I
10.1109/ESSDER.2005.1546661
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We report a high performance NFET with a HfO2/TiN gate stack showing high field (1 MV/cm) D.C. mobility of 194 cm(2)/V-s (80% univ. SiO2) and peak D.C. mobility of 239 cm(2)/V-s at EOT=9.5 angstrom. These mobility results are among the best reported for HfO2 with sub-10 angstrom EOT and represent a potential gate dielectric solution for 45 nm CMOS technologies. A 2x mobility improvement was realized by thinning HfO2 from T-phys=4.0 nm to 2.0 nm. The mechanism for mobility improvement is shown to be reduced transient charge trapping. Issues associated with scaling HfO2 including film continuity, density and growth incubation are studied with low energy ion scattering (LEIS), X-ray reflectivity (XRR) and Rutherford backscattering (RBS) and indicate atomic layer deposition (ALD) HfO2 can scale below T-phys=2.0 nm. While the mobility advancement with 2.0 nm HfO2 is important, an additional concurrent advancement is improved V, stability. Constant voltage stress results show AV, improves 2x after 1000s stress at 1.8V as thickness is reduced in the range 2.0-4.0 nm.
引用
收藏
页码:367 / 370
页数:4
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