Hardware realization of Krawtchouk transform using VHDL modeling and FPGAs

被引:7
作者
Botros, NM [1 ]
Yang, J
Feinsilver, P
Schott, R
机构
[1] So Illinois Univ, Dept Elect Engn, Carbondale, IL 62901 USA
[2] So Illinois Univ, Dept Math, Carbondale, IL 62901 USA
[3] Zycad Corp, Fremont, CA 93536 USA
[4] Univ Nancy 1, Ctr Rech Informat Nancy, F-54506 Vandoeuvre Les Nancy, France
关键词
field-programmable gate arrays (FPGAs); image compression; Krawtchouk transform; modeling and simulation; system on a chip; Very High Speed Integrated Circuit Hardware; Descriptive Language (VHDL); wavelets;
D O I
10.1109/TIE.2002.804984
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we present a hardware realization of a simplified Krawtchouk transform. The transform is realized on a Xilinx Field-programmable gate arrays chip. The hardware is stand-alone and operates on a real-time basis. Very High Speed Integrated Circuit Hardware Descriptive Language structural, behavioral, and data flow modeling are implemented to describe, simulate, and realize the transform. The hardware consists mainly of an 8 x 8-2's-complement multiplier, a 16-b accumulator, a 16 x 16-b RAM, a 64 x 8-b ROM, and a microprogram-based control unit. A brief analysis of the transform and a contrast between its hardware and that of Fourier transform are presented. The hardware is tested by inputting an eight-point data vector to the input pins of the chip. The results of the transform are read from the output pins of the chip. The results are compared with those obtained from a software program executing the same transform for the same input data vector as the hardware. It is found that results from the hardware match those of the software.
引用
收藏
页码:1306 / 1312
页数:7
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