Memory-aware dynamic voltage scaling for multimedia applications

被引:9
作者
Choi, J [1 ]
Cha, H [1 ]
机构
[1] Yonsei Univ, Dept Comp Sci, Seoul 120749, South Korea
来源
IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES | 2006年 / 153卷 / 02期
关键词
D O I
10.1049/ip-cdt:20050031
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 [计算机科学与技术];
摘要
As the computing environments are continuously moving towards battery-operated mobile and handheld systems, the development of energy-saving mechanisms for such devices has recently become a technical challenge. Dynamic voltage scaling (DVS) has historically been considered an effective method to reduce the processor power consumption. Conventional DVS techniques typically consider only processor utilisation issues in a policy-making process. However, as memory-bound multimedia applications are becoming popular in handheld devices, the DVS policies should consider the so-called 'memory wall' problem to maximise energy gain. Recent DVS techniques suffer from the inefficiency of their policies caused by the memory-wall problem while executing multimedia applications, and no previous research on DVS considers the problem explicitly. The existence of the memory wall problem in a real system is revealed and a metric that can be used to detect the problem in advance is found. A memory-aware DVS (M-DVS) technique that takes the memory wall problem fully into consideration is proposed. The experimental results on a PDA show that M-DVS can reduce similar to 8% of additional power consumption, compared with conventional DVS, without any QoS degradation for handling multimedia clips.
引用
收藏
页码:130 / 136
页数:7
相关论文
共 17 条
[1]
*AG, 2005, 34970A AG
[2]
Cho YJ, 2004, ISLPED '04: PROCEEDINGS OF THE 2004 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P387
[3]
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding [J].
Choi, K ;
Soma, R ;
Pedram, M .
41ST DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2004, 2004, :544-549
[4]
FAN X, 2003, P WORKSH POW AW COMP, P164
[5]
Govil K., 1995, P 1 ANN INT C MOB CO, P13, DOI DOI 10.1145/215530.215546
[6]
GRUNWALD D, 2000, P 4 S OP SYST DES IM
[7]
Hennessy John L., 2003, COMPUTER ARCHITECTUR
[8]
*INT, INT PXA27X PROC FAM
[9]
Nonideal battery and main memory effects on CPU speed-setting for low power [J].
Martin, TL ;
Siewiorek, DP .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2001, 9 (01) :29-34
[10]
MARTIN TL, 2003, ACM T EMBED COMPUT S, V2, P255