A 60-ns 1-Mb nonvolatile ferroelectric memory with a nondriven cell plate line write/read scheme

This paper proposes three circuit technologies for achieving mega-bit-class nonvolatile ferroelectric RAM's (NVFRAM's), The proposed nondriven cell plate line write/read scheme (NDP scheme) accomplishes fast write/read operation equivalent to that of DRAM's, Problems and countermeasures in introducing this scheme into NVFRAM's are also discussed, A proposed optimized C-B/C-S cell array design method provides a relationship between bit line capacitance C-B and memory cell capacitance C-S, which must be satisfied for read operations, Also reported is a reference voltage generator circuit that uses a dummy memory cell, This circuit can generate an accurate reference voltage despite the variety of capacitors with differing characteristics that are contained in the NVFRAM, A 1-Mb NVFRAM prototype featuring the above technologies has been fabricated, using a 1.0-mu m CMOS process, This chip has an access time of 60 ns and a die size of 15.7 x 5.79 mm(2).