A 512 Kbit low-voltage NV-SRAM with the size of a conventional SRAM

被引：18

作者：

Miwa, T ^{[1
]}

Yamada, J ^{[1
]}

Koike, H ^{[1
]}

Nakura, T ^{[1
]}

Kobayashi, S ^{[1
]}

Kasai, N ^{[1
]}

Toyoshima, H ^{[1
]}

机构：

[1] NEC Corp Ltd, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291198, Japan

来源：

2001 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VLSIC.2001.934217

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes two new circuit techniques for nonvolatile SRAMs with back-up ferroelectric capacitors (NV-SRAMs). These circuits are able to overcome the size and low-voltage-reliability problems faced by the original NV-SRAM. A new 0.25-mum-design-rule four-metal-layer NV-SRAM cell occupies 9.7 mum(2), that is the same area as a 0.25-mum three-metal-layer SRAM cell. A high-voltage/negative-voltage plate line driver allows a low-voltage-operation NV-SRAM array's improving its nonvolatile retention characteristics, A 512-Kbit-test macro has also been designed with only one percent area overhead from a conventional SRAM macro.

引用

页码：129 / 132

页数：4

共 4 条

[1] Capacitor-on-Metal/Via-stacked-Plug (CMVP) memory cell for 0.25 μm CMOS embedded FeRAM [J].

Amanuma, K ;

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Maejima, Y ;

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Hada, H ;

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Kunio, T .

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[2]

AMANUMA K, 1999, SSDM SEP, P384

[3] NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors [J].

Miwa, T ;

Yamada, J ;

Koike, H ;

Toyoshima, H ;

Amanuma, K ;

Kobayashi, S ;

Tatsumi, T ;

Maejima, Y ;

Hada, H ;

Kunio, T .

PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2000, :65-68

[4]

MIWA T, IN PRESS J SOLID STA

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