Capacitor-on-Metal/Via-stacked-Plug (CMVP) memory cell for 0.25 μm CMOS embedded FeRAM

被引：41

作者：

Amanuma, K ^{[1
]}

Tatsumi, T ^{[1
]}

Maejima, Y ^{[1
]}

Takahashi, S ^{[1
]}

Hada, H ^{[1
]}

Okizaki, H ^{[1
]}

Kunio, T ^{[1
]}

机构：

[1] NEC Corp Ltd, Silicon Syst Res Labs, Sagamihara, Kanagawa 2291198, Japan

来源：

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST | 1998年

关键词：

D O I：

10.1109/IEDM.1998.746375

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A Capacitor-on-Meta/Via-stacked-Plug (CMVP) memory cell was developed for 0.25 mu m CMOS logic embedded FeRAM. Using 445 degrees C MOCVD Pb(Zr,Ti)O-3 process, a ferroelectric capacitor is formed after CMOS logic fabrication. Thus, FeRAM can be embedded without changing any logic devices and processes. Furthermore, this technology enables the cell size reduction (3.2 mu m(2) for 1T1C), the minimum process damage on ferroelectric, and low manufacturing cost.

引用

页码：363 / 366

页数：4

共 4 条

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