Cascaded voting process for flash ADC with interpolating scheme

被引：5

作者：

Jang, Y. -C. ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Hwasung City, Gyeonggi Do, South Korea

来源：

ELECTRONICS LETTERS | 2008年 / 44卷 / 18期

关键词：

D O I：

10.1049/el:20080499

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 3-stage cascaded voting process is proposed for. ash analogue-to-digital converters (ADCs) with an interpolation factor of 4 to eliminate the consecutive bubbles at the output nodes of the comparator array. Compared to the conventional 3-input voting process, the proposed process completely eliminates up to seven consecutive bubbles without hardware overhead, if the preamplifier output is assumed to have a single bubble at most. The proposed voting process is evaluated by 7-bit 1 GS/s CMOS. ash ADCs with an interpolation factor of 4 which is designed by a 0.13 mu m CMOS process with 1.2 V supply.

引用

页码：1047 / U2

页数：2