A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS

被引：180

作者：

Choi, M ^{[1
]}

Abidi, AA ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2001年 / 36卷 / 12期

关键词：

A/D converter; CMOS analog integrated circuits; comparators; flash converter; offset averaging; read channel; resistor averaging network; spatial filter; track-and-hold;

D O I：

10.1109/4.972135

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1 Gsample/s. The chip occupies 0.8-mm(2) active area, fabricated in 0.35-mum CMOS.

引用

页码：1847 / 1858

页数：12

共 41 条

[1]

AKAZAWA Y, 1987, ISSCC, P98

[2]

Altekar S., 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), P184, DOI 10.1109/ISSCC.2001.912596

[3] THE DESIGN OF SIGMA-DELTA MODULATION ANALOG-TO-DIGITAL CONVERTERS [J].

BOSER, BE ;

WOOLEY, BA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (06) :1298-1308

[4] An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm(2) [J].

Bult, K ;

Buchwald, A .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (12) :1887-1895

[5]

CHOI M, 2001, IEEE INT SOL STAT CI, P126

[6] A 200-MSPS 6-bit flash ADC in 0.6-μm CMOS [J].

Dalton, D ;

Spalding, GJ ;

Reyhani, H ;

Murphy, T ;

Deevy, K ;

Walsh, M ;

Griffin, P .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (11) :1433-1444

[7] DUMMY TRANSISTOR COMPENSATION OF ANALOG MOS SWITCHES [J].

EICHENBERGER, C ;

GUGGENBUHL, W .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (04) :1143-1146

[8]

FLYNN M, 1998, ISSCC, P150

[9] A DUAL 4-BIT 2-GS S FULL NYQUIST ANALOG-TO-DIGITAL CONVERTER USING A 70-PS SILICON BIPOLAR TECHNOLOGY WITH BOROSENIC POLY PROCESS AND COUPLING-BASE IMPLANT [J].

GARUTS, VE ;

YU, YCS ;

TRAA, EO ;

YAMAGUCHI, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (02) :216-222

[10]

GEELEN G, 2001, IEEE INT SOL STAT CI, P128

← 1 2 3 4 5 →