Threshold voltage roll-up/roll-off characteristic control in sub-0.2-μm single workfunction gate CMOS for high-performance DRAM applications

Threshold voltage (V-t) roll-off/roll-up control is a key issue to achieve high-performance sub-0.2-mum single workfunction gate CMOS devices for high-speed DRAM applications. It is experimentally confirmed that a combination of well RTA and N-2 implant prior to gate oxidation is important to reduce V-t roll-up characteristics both in nFET and pFET. Optimization of RTA conditions after source/drain (S/D) implant is also discussed as a means of improving V-t roll-off characteristics. Finally, the impact of halo implant on V-t variation in sub-0.2-mum buried channel pFETs is discussed. It is found that halo profile control is necessary for tight V-t variation in sub-0.2-mum single workfunction gate pFET.