Investigating the performance limits of silicon-nanowire and carbon-nanotube FETs

被引：40

作者：

Marchi, A ^{[1
]}

Gnani, E ^{[1
]}

Reggiani, S ^{[1
]}

Rudan, M ^{[1
]}

Baccarani, G ^{[1
]}

机构：

[1] Univ Bologna, DEIS, Dept Elect, ARCES, I-40136 Bologna, Italy

来源：

SOLID-STATE ELECTRONICS | 2006年 / 50卷 / 01期

关键词：

electrostatic analysis; quantum-mechanical simulation; silicon nanowire; carbon nanotube;

D O I：

10.1016/j.sse.2005.10.039

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this work we investigate and compare the electrostatics of fully depleted cylindrical silicon-nanowire (SiCNW) FETs, four-gate rectangular nanowire (4G RNW) FETs, tri-gate rectangular nanowire (3G RNW) FETs and gate-all-around carbon-nanotube (GAA-CNT) FETs at advanced miniaturization limits. In doing so, we rigorously solve the coupled Schrodinger-Poisson equations within the device cross-sections and fully account for quantum-mechanical effects. The investigation, carried out for the 65 and 45 nm technology nodes, leads to the unexpected conclusion that, for an assigned threshold voltage, the gate-all-around CNT-FET offers only a slightly better performance with respect to the SiCNW and the 4G RNW-FETs. This is due to the compensation of two different mechanisms, namely a higher gate effectiveness and a lower density of states. The 3G RNW yields instead an electron density within the channel which is about 25% lower than the SiCNW and 4G RNW-FETs at a given gate voltage. Such a reduced performance is due to its inherent asymmetry, which negatively affects the gate control on the channel charge. (c) 2005 Elsevier Ltd. All rights reserved.

引用

页码：78 / 85

页数：8

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