Design and analysis of high-speed random access memory with Coulomb blockade charge confinement

被引：11

作者：

Katayama, K ^{[1
]}

Mizuta, H ^{[1
]}

Müller, HO ^{[1
]}

Williams, D ^{[1
]}

Nakazato, K ^{[1
]}

机构：

[1] Hitachi Europe Ltd, Hitachi Cambridge Lab, Cambridge CB3 OHE, England

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1999年 / 46卷 / 11期

关键词：

cell design; Coulomb blockade; high-speed RAM; simulation; single electron;

D O I：

10.1109/16.796298

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A silicon-based memory cell utilizing Coulomb blockade is analyzed for use as a high-speed RAM. Operation principles and design guidelines are given by simple analytical modeling and simulations. By performing transient waveform Monte Carlo simulations, high-speed write operation is demonstrated with a time shorter than 10 ns, The memory node voltage of less than 0.1 V is detected by a newly proposed split-gate cell structure with a minimum disturbance to/from nonselected cells, which indicates the compatibility of this structure with conventional field effect transistors.

引用

页码：2210 / 2216

页数：7

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