Performance improvement of metal gate CMOS technologies

被引：18

作者：

Matsuda, S ^{[1
]}

Yamakawa, H ^{[1
]}

Azuma, A ^{[1
]}

Toyoshima, Y ^{[1
]}

机构：

[1] Toshiba Co Ltd, Semicond Co, Syst LSI Res & Dev Ctr, Isogo Ku, Yokohama, Kanagawa 2358522, Japan

来源：

2001 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2001年

关键词：

D O I：

10.1109/VLSIT.2001.934948

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

Metal gate CMOS technologies for high speed application was investigated using damascene metal gate process [1]. We demonstrated the performance improvement by no gate depletion effect of metal gate using actual device. Ti/W was used as single work function metal gate material and ultra shallow buried channel profile was formed for threshold voltage control. Self-aligned channel structure effectively reduces source/drain junction capacitance. Extremely good metal/SiO2 interface with CVD-TiN gate stack realizes intrinsic channel mobility. Propagation delay time of CMOS inverter ring oscillator was 20 ps, and projected performance in next generation would be better using improved technologies.

引用

页码：63 / 64

页数：2

共 6 条

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