Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications

被引：34

作者：

Brisbin, D ^{[1
]}

Strachan, A ^{[1
]}

Chaparala, P ^{[1
]}

机构：

[1] Natl Semicond Corp, Santa Clara, CA 95052 USA

来源：

40TH ANNUAL PROCEEDINGS: INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM | 2002年

关键词：

D O I：

10.1109/RELPHY.2002.996617

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper evaluates the hot carrier performance of n-channel lateral DMOS (N-LDMOS) transistors. The N-LDMOS has been the common choice for the driver transistor in high voltage (20-30 V) smart power applications. These high drain voltages potentially make N-LDMOS hot carrier degradation an important reliability concern. This paper focuses on the hot carrier test methodology and Geometry effects in N-LDMOS transistor arrays. This paper differs from previous work in that it describes for the first time the HC performance of N-LDMOS transistor arrays rather than discrete devices and discusses an N-LDMOS failure mode not yet addressed in the literature.

引用

页码：105 / 110

页数：6

共 8 条

[1] CONSISTENT MODEL FOR THE HOT-CARRIER DEGRADATION IN N-CHANNEL AND P-CHANNEL MOSFETS [J].