An input-free V-T extractor circuit using a series connection of three transistors

This paper describes a self-biased MOS transistor circuit with the ground referenced output voltage equal to the threshold voltage V-T. The circuit employs a series connection of three transistors where the middle transistor is in linear operation and external transistors are in saturation. The circuit can be applied for V-T extraction of both n-channel and p-channel transistors. The range of currents for better measuring of V-T in each case is established by simulation.