Development of a pixel readout chip for BTeV

被引:32
作者
Christian, DC [1 ]
Appel, JA [1 ]
Cancelo, G [1 ]
Kwan, S [1 ]
Hoff, J [1 ]
Mekkaoui, A [1 ]
Srage, J [1 ]
Yarema, R [1 ]
Zimmermann, S [1 ]
机构
[1] Fermi Natl Accelerator Lab, Batavia, IL 60510 USA
关键词
D O I
10.1016/S0168-9002(99)00421-0
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
A description is given of the R&D program underway at Fermilab to develop a pixel readout ASIC appropriate for use at the Tevatron collider. Results are presented from tests performed on the first prototype pixel readout chip designed at Fermilab, and a new readout architecture is described. (C) 1999 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:144 / 152
页数:9
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