Synergistic processing in Cell's multicore architecture

被引：194

作者：

Gschwind, M

Hofstee, HP

Flachs, B

Watanabe, Y

Yamazaki, T

机构：

[1] IBM Corp, Thomas J Watson Res Ctr, Yorktown Hts, NY 10598 USA

[2] IBM Austin, Cell BE, Synergist Processor Element Architecture, Austin, TX USA

[3] Toshiba Co Ltd, Kawasaki, Kanagawa 210, Japan

[4] Sony Comp Entertainment, Microprocessor Dev Div, Leeds, W Yorkshire, England

来源：

IEEE MICRO | 2006年 / 26卷 / 02期

关键词：

D O I：

10.1109/MM.2006.41

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Eight synergistic processor units enable the cell broadband engine's breakthrough performance. The SPU architecture implements a novel, pervasively data-parallel architecture combining scalar and simd processing on a wide data path. A large number of spus per chip provide high thread-level parallelism.

引用

页码：10 / 24

页数：15

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