共 23 条
[1]
Burger D, 1997, 1342 U WISC MAD COMP
[2]
BUTLER M, 1991, ACM COMP AR, V19, P276, DOI 10.1145/115953.115980
[3]
Ding-Kai Chen, 1994, Proceedings of the 1994 International Conference on Parallel Processing, P24
[4]
Dubey P. K., 1995, Parallel Architectures and Compilation Techniques. Proceedings of the IFIP WG10.3 Working Conference. PACT'95, P109
[5]
Fillo M., 1995, Proceedings of the 28th Annual International Symposium on Microarchitecture (Cat. No.95TB100012), P146, DOI 10.1109/MICRO.1995.476822
[6]
FRANKLIN M, 1992, ACM COMP AR, V20, P58, DOI 10.1145/146628.139703
[7]
HIRATA H, 1992, ACM COMP AR, V20, P136, DOI 10.1145/146628.139710
[8]
An efficient strategy for developing a simulator for a novel concurrent multithreaded processor architecture
[J].
SIXTH INTERNATIONAL SYMPOSIUM ON MODELING, ANALYSIS AND SIMULATION OF COMPUTER AND TELECOMMUNICATION SYSTEMS, PROCEEDINGS,
1998,
:185-191
[9]
Johnson Mike, 1991, Superscalar Microprocessor Design
[10]
LAM MS, 1992, ACM COMP AR, V20, P46, DOI 10.1145/146628.139702