A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-mum CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first EF of 190 MHz best tolerates blocking signals. The receiver includes all of circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meet GSM phase-noise specifications.