High room temperature peak-to-valley current ratio in Si based Esaki diodes

被引：41

作者：

Duschl, R

Schmidt, OG

Reitemann, G

Kasper, E

Eberl, K

机构：

[1] Max Planck Inst Festkorperforsch, D-70569 Stuttgart, Germany

[2] Univ Stuttgart, Inst Halbleitertech, D-70569 Stuttgart, Germany

来源：

ELECTRONICS LETTERS | 1999年 / 35卷 / 13期

关键词：

D O I：

10.1049/el:19990728

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Room temperature (RT) I-V characteristics of epitaxially group Si/SiGe/Si p(+)/i/n(+) Esaki diodes are presented. The incorporation of Ge within the intrinsic (i) zone gives rise to an increased peak current density (j(P) = 3kA/cm(2)) and peak-to-valley current ratio (PVCR) compared to pure Si structures (j(P) = 80A/cm(2)). A detailed investigation and optimisation of post-growth annealing has demonstrated a record PVCR of 4.2 for Si based Esaki diodes.

引用

页码：1111 / 1112

页数：2

共 6 条

[1] AN ALLOY PROCESS FOR MAKING HIGH CURRENT DENSITY SILICON TUNNEL DIODE JUNCTIONS [J].