Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors - Chip design and system implementation

被引：5

作者：

Kunzia, CB ^{[1
]}

Wu, JM ^{[1
]}

Chen, CH ^{[1
]}

Hoanca, B ^{[1
]}

Cheng, L ^{[1
]}

Weber, AG ^{[1
]}

Sawchuk, AA ^{[1
]}

机构：

[1] Univ So Calif, Inst Signal & Image Proc, Los Angeles, CA 90089 USA

来源：

IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS | 1999年 / 5卷 / 02期

基金：

美国国家科学基金会;

关键词：

cellular logic arrays; CMOS integrated circuits; integrated optoelectronics; optical interconnections; smart pixels;

D O I：

10.1109/2944.778326

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical nearest-neighbor local interconnections. The smart pixels are implemented using GaAs-GaAlAs multiple quantum-well diode arrays flip-chip bonded onto complementary metal-oxide-semiconductor circuitry through the Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry, This system provides efficient execution of single-instruction multiple-data algorithms on large data fields and images.

引用

页码：376 / 386

页数：11