A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

A fully integrated CMOS frequency synthesizer for PCS- and cellular-CDMA systems is integrated in a 0.35-mum CMOS technology. The proposed charge-averaging charge pump scheme suppresses fractional spurs to the level of noise, and the improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. With current-feedback bias and coarse tuning, a voltage-controlled oscillator (VCO) enables constant power and low gain of the VCO. Power dissipation is 60 mW with a 3.0-V supply. The proposed frequency synthesizer provides 10-kHz channel spacing with phase noise of -121 dBc/Hz in the PCS band and -127 dBc/Hz in the cellular band, both at 1-MHz offset frequency.