Powering networks on chips - Energy-efficient and reliable interconnect design for SoCs

被引：70

作者：

Benini, L ^{[1
]}

De Micheli, G ^{[1
]}

机构：

[1] Univ Bologna, DEIS, I-40136 Bologna, Italy

来源：

ISSS'01: 14TH INTERNATIONAL SYMPOSIUM ON SYSTEM SYNTHESIS | 2001年

关键词：

systems on chips; low-energy design; networks;

D O I：

10.1109/ISSS.2001.957909

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We consider systems on chips (SoCs) that will be designed and produced in five to tell years front today, with gate lengths in the range 50-100nm. We address the distinguishing features of a design methodology that aims at achieving reliable designs tinder the limitations of the interconnect technology. Specifically, we consider energy consumption reduction, under guaranteed quality of service (QoS), as a main objective in system design.

引用

页码：33 / 38

页数：6

共 22 条

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