Relationship between gate lag, power drift, and power slump of pseudomorphic high electron mobility transistors

This paper attempts to clarify the confusion between different surface-related problems of PHEMTs such as gate lag, power drift, and power slump. Distinguishment is made not only in terms of electrical characteristics but also physical mechanisms. It was found that gate lag can be attributed to surface states while power drift and slump can be attributed to recoverable and irrecoverable, respectively, charge buildups in the silicon-nitride surface-passivation layer. As the result, the worsening of gate lag instead of gate lag per se can be an indicator of power drift while power drift can be a precursor for power slump. Based on such an understanding, a convenient screening test for these surface-related problems is proposed. (C) 1999 Elsevier Science Ltd. All rights reserved.