μtrench phase-change memory cell engineering and optimization

被引：12

作者：

Pirovano, A ^{[1
]}

Pellizzer, F ^{[1
]}

Redaelli, A ^{[1
]}

Tortorelli, I ^{[1
]}

Varesi, E ^{[1
]}

Ottogalli, F ^{[1
]}

Tosi, M ^{[1
]}

Besana, P ^{[1
]}

Cecchini, R ^{[1
]}

Piva, R ^{[1
]}

Magistretti, M ^{[1
]}

Scaravaggi, M ^{[1
]}

Mazzone, G ^{[1
]}

Petruzza, P ^{[1
]}

Bedeschi, F ^{[1
]}

Marangon, T ^{[1
]}

Modelli, A ^{[1
]}

Ielmini, D ^{[1
]}

Lacaita, AL ^{[1
]}

Bez, R ^{[1
]}

机构：

[1] STMicroelectronics, Adv R&D, Mon Volatile Memories Technol Dev, Frontend Technol & Mfg, I-20041 Agrate Brianza, Mi, Italy

来源：

PROCEEDINGS OF ESSDERC 2005: 35TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSDER.2005.1546648

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Phase-Change Memory (PCM) cell is the most promising technology as post-Flash Non-Volatile memory (NVM). Among the different proposed cell structures, mu trench allows to simultaneously achieve low programming currents, small cell size, easy tunability and good dimensional control. Aim of this paper is to investigate the optimization and fine tuning capability of this cell architecture. Based on theoretical analysis and experimental results, the dependence of the PCM electrical parameters on the cell structure and on the geometric dimensions is assessed. An optimized mu trench cell with a programming current of 450 mu A at 1.5 V and a set resistance of 5 k Omega is finally presented.

引用

页码：313 / 316

页数：4

共 9 条

[1] Highly manufacturable high density phase change memory of 64Mb and beyond [J].

Ahn, SJ ;

Song, YJ ;

Jeong, CW ;

Shin, JM ;

Fai, Y ;

Hwang, YN ;

Lee, SH ;

Ryoo, KC ;

Lee, SY ;

Park, JH ;

Horii, H ;

Ha, YH ;

Yi, JH ;

Kuh, BJ ;

Koh, GH ;

Jeong, GT ;

Jeong, HS ;

Kim, K ;

Ryu, BI .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :907-910

[2]

HA YH, 2003, VLSI S

[3]

Lacaita AL, 2004, IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, P911

[4]

Lai S, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P255

[5] Low-cost and nanoscale non-volatile memory concept for future silicon chips [J].

Lankhorst, MHR ;

Ketelaars, BWSMM ;

Wolters, RAM .

NATURE MATERIALS, 2005, 4 (04) :347-352

[6]

MERGET F, 2004, NVSMW 04, P30

[7]

Pellizzer F, 2004, 2004 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, P18

[8] Reliability study of phase-change nonvolatile memories [J].

Pirovano, A ;

Redaelli, A ;

Pellizzer, F ;

Ottogalli, F ;

Tosi, M ;

Ielmini, D ;

Lacaita, AL ;

Bez, R .

IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, 2004, 4 (03) :422-427

[9]

Pirovano A, 2003, 2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, P699

← 1 →