Discrete wavelet transform: Data dependence analysis and synthesis of distributed memory and control array architectures

被引:27
作者
Fridman, J [1 ]
Manolakos, ES [1 ]
机构
[1] NORTHEASTERN UNIV,COMMUN & DIGITAL SIGNAL PROC CTR,DEPT ELECT & COMP ENGN,BOSTON,MA 02115
关键词
D O I
10.1109/78.575701
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, we perform a thorough data dependence and localization analysis for the discrete wavelet transform algorithm and then use it to synthesize distributed memory and control architectures for its parallel computation, The discrete wavelet transform (DWT) is characterized by a nonuniform data dependence structure owing to the decimation operation (it is neither a uniform recurrence equation (URE) nor an affine recurrence equation (ARE) and consequently cannot be transformed directly using linear space-time mapping methods into efficient array architectures, Our approach is to apply first appropriate nonlinear transformations operating on the algorithm's index space, leading to a new DWT formulation on which application of Linear space-time mapping can become effective, The first transformation of the algorithm achieves regularization of interoctave dependencies but alone does not lead to efficient array solutions after the mapping due to limitations associated with transforming three-dimensional (3-D) algorithm onto one-dimensional (1-D) arrays, which is also known as multiprojection, The second transformation is introduced to remove the need for multiprojection by formulating the regularized DWT algorithm in a two-dimensional (2-D) index space, Using this DWT formulation,,ve have synthesized two VLSI-amenable linear arrays of L PE's computing a J-octave DWT decomposition with latencies of M and 2M-1, respectively, where L is the wavelet filter length, and M is the number of samples in the data sequence, The arrays are modular, regular, use simple control, and can be easily extended to larger L and J. The latency of both arrays is independent of the highest octave J, and the efficiency is nearly 100% for any M with one design achieving the lowest possible latency of M.
引用
收藏
页码:1291 / 1308
页数:18
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