Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

被引：140

作者：

Karim, KS ^{[1
]}

Nathan, A

Hack, M

Milne, WI

机构：

[1] Simon Fraser Univ, Sch Engn Sci, Burnaby, BC V5A 1S6, Canada

[2] Univ Waterloo, Waterloo, ON N2L 3G1, Canada

[3] Universal Display Corp, Ewing, NJ 08618 USA

[4] Univ Cambridge, Dept Engn, Cambridge CB2 1PZ, England

来源：

IEEE ELECTRON DEVICE LETTERS | 2004年 / 25卷 / 04期

关键词：

amorphous silicon; thin-film transistor (TFT); threshold voltage; metastability;

D O I：

10.1109/LED.2004.825154

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V-T) stability performance. At small gate stress voltages (0 less than or equal to V-ST less than or equal to 15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V-T(DeltaV(T)) compared to the DeltaV(T) in the absence of a drain bias. The measured shift in VT appears to agree with the defect pool model that the DeltaV(T) is proportional to the number of induced carriers in the a-Si:H channel.

引用

页码：188 / 190

页数：3

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