SiGeBiCMOS technology with 3.0 ps gate delay

被引:12
作者
Ruecker, H. [1 ]
Heinemann, B. [1 ]
Barth, R. [1 ]
Bauer, J. [1 ]
Blum, K. [1 ]
Bolze, D. [1 ]
Drews, J. [1 ]
Fischer, G. G. [1 ]
Fox, A. [1 ]
Fursenko, O. [1 ]
Grabolla, T. [1 ]
Haak, U. [1 ]
Hoeppner, W. [1 ]
Knoll, D. [1 ]
Koepke, K. [1 ]
Kuck, B. [1 ]
Mai, A. [1 ]
Marschmeyer, S. [1 ]
Morgenstern, T. [1 ]
Richter, H. H. [1 ]
Schley, P. [1 ]
Schmidt, D. [1 ]
Schulz, K. [1 ]
Tillack, B. [1 ]
Weidner, G. [1 ]
Winkler, W. [1 ]
Wolansky, D. [1 ]
Wulf, H. E. [1 ]
Yamamototo, Y. [1 ]
机构
[1] IHP, D-15236 Frankfurt, Oder, Germany
来源
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年
关键词
D O I
10.1109/IEDM.2007.4419028
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
This work reports on a 130 nm BiCMOS technology with high-speed SiGe:C HBTs featuring a transit frequency of 255 GHz and a maximum oscillation frequency of 315 GHz at an emitter area of 0.17 x 0.53 mu m(2). A minimum gate delay of 3.0 ps was achieved for CML ring oscillators. Breakdown voltages of the HBTs are measured to be BV(CEO)=1.8 V, BV(CBO)=5.6 V, and BV(EBO)=1.9 V.
引用
收藏
页码:651 / 654
页数:4
相关论文
共 7 条
[1]  
BOCK J, 2004, 3 3 PS SIGE BIPOLAR, P255
[2]  
HEINEMANN B, 2004, LOW PARASITIC COLLEC, P251
[3]   3.21 ps ECL gate using InP/InGaAs DHBT technology [J].
Ishii, K ;
Nosaka, H ;
Ida, M ;
Kurishima, K ;
Shibata, T .
ELECTRONICS LETTERS, 2003, 39 (20) :1434-1436
[4]  
KHATER M, 2004, SIGE HBT TECHNOLOGY, P247
[5]  
LEE S, VLSI S 2007
[6]  
RUCKER H, 2003, SIGE C BICMOS TECHNO, P121
[7]  
VANHUYLENBROECK S, 2006, 205 275 GHZ FT FMAX