A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSix storage nodes for Gb-scale DRAM's

被引：38

作者：

Yamamichi, S

Lesaicherre, PY

Yamaguchi, H

Takemura, K

Sone, S

Yabuta, H

Sato, K

Tamura, T

Nakajima, K

Ohnishi, S

Tokashiki, K

Hayashi, Y

Kato, Y

Miyasaka, Y

Yoshida, M

Ono, H

机构：

[1] NEC CORP LTD,ULSI DEVICE DEV LABS,SAGAMIHARA,KANAGAWA 229,JAPAN

[2] SEMICOND LEADING EDGE TECHNOL,TOKYO 101,JAPAN

[3] NEC CORP LTD,MICROELECT RES LABS,SAGAMIHARA,KANAGAWA 229,JAPAN

[4] NEC CORP LTD,MICROELECT RES LABS,TSUKUBA,IBARAKI 305,JAPAN

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1997年 / 44卷 / 07期

关键词：

Dielectric devices - Dielectric materials - Electron beam lithography - Metallorganic chemical vapor deposition - Reactive ion etching;

D O I：

10.1109/16.595934

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO3 thin films is described, The four-layer RuO2/Ru/TiN/TiSix storage node configuration allows 500 degrees C processing and fine-patterning down to the 0.20 mu m size by electron beam lithography and reactive ion etching, Good insulating (Ba0.4Sr0.6)TiO3 (BST) films with an SiO2 equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1 x 10(-6) A/cm(2) at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing. A lateral step coverage of 50% for BST is observed on the 0.2 mu m size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma, Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAM's can be achieved in a capacitor area of 0.125 mu m(2) with only the 0.3 mu m high-storage electrodes.

引用

页码：1076 / 1083

页数：8

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