A 0.9-V, 150-MHz, 10-mW, 4 mm(2), 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

A 4 mm(2), two-dimensional (2 D) 8 x 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-mu m CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V-DD - V-th design space is also studied.