LIMITATION OF CMOS SUPPLY-VOLTAGE SCALING BY MOSFET THRESHOLD-VOLTAGE VARIATION

A fundamental limit of CMOS supply-voltage (V-cc) scaling has been investigated and quantified as a function of the statistical variation of MOSFET threshold-voltage (V-T). Based on the data extracted from a sub-0.5 mu m logic technology, the variation of ring-oscillator propagation-delay (T-pd) significantly increases as V-cc is scaled down towards the MOSFET V-T. An empirical power-law relationship was then derived to describe the scattering of circuit speed (Delta T-pd) as a function of MOSFET V-T variation (Delta V-T) and (V-cc - V-T). Agreement between the model and the experimental data was established for V-cc values from 4.0 to 0.9 V. This fundamental limit of CMOS V-cc scaling poses an additional challenge for the design and manufacturing of high-performance, low-power portable systems and battery-based equipments.