A FULLY COMPLEMENTARY BICMOS TECHNOLOGY FOR SUB-HALF-MICROMETER MICROPROCESSOR APPLICATIONS

A modular process architecture has been adopted to develop a versatile yet manufacturable, single-poly, four-level metal, fully complementary BiCMOS technology for sub-0.5-mum microprocessor products. Both the poly-emitter vertical n-p-n and p-n-p bipolar transistors are integrated into a dual-poly (n+/p+) gate CMOS process flow. Using a collector pedestal implant in the emitter window, the n-p-n performance has been enhanced to 26 GHz. Lateral p-n-p and TiSi2 Schottky-barrier diode are also available for circuit applications. Stacking of the tungsten-plug contacts and vias are allowed in the multilevel metallization module. Comparing the CMOS and BiCMOS implementations of a 68030 critical path, 40% speed improvement at 3.3-V V(cc) and a CMOS/BiCMOS crossover at 2.2 V have been obtained for this logic BiCMOS technology.