A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology

被引:110
作者
Lam, C [1 ]
Razavi, B [1 ]
机构
[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA
关键词
frequency dividers; oscillators; phase-locked loops; RF circuits; synthesizers; wireless transceivers;
D O I
10.1109/4.841508
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the design of a CMOS frequency synthesizer targeting wireless local-area network applications in the 5-GHz range, Based on an integer-IV architecture, the synthesizer produces a 5.2-GHz output as well as the quadrature phases of a 2.6-GHz carrier. Fabricated in a 0.4-mu m digital CMOS technology, the circuit provides a channel spacing of 23.5 MHz at 5.2 GHz while exhibiting a phase noise of -115 dBc/Hz at 2.6 GHz and -100 dBc/Hz at 5.2 GHz (both at 10-MHz offset). The reference sidebands are at -53 dBc at 2.6 GHz, and the power dissipation from a 2.6-V supply is 47 mW.
引用
收藏
页码:788 / 794
页数:7
相关论文
共 8 条
[1]   A WIDE-BANDWIDTH LOW-VOLTAGE PLL FOR POWERPC(TM) MICROPROCESSORS [J].
ALVAREZ, J ;
SANCHEZ, H ;
GEROSA, G ;
COUNTRYMAN, R .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (04) :383-391
[2]  
COUCH LW, 1993, DIGITAL ANAL COMMUNI
[3]   A fully integrated CMOS DCS-1800 frequency synthesizer [J].
Craninckx, J ;
Steyaert, MSJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) :2054-2065
[4]  
*ETSI TC RES, 1995, RAD EQ SYST RES HIGH
[5]  
MERRIL RB, 1995, P IEDM DEC
[6]  
RAZAVI B, 1997, IEEE INT SOL STAT CI, P388
[7]  
Razavi B, 2011, RF Microelectronics, V2nd
[8]  
ROFOUGARAN A, 1996, IEEE INT SOL STAT CI, P392