A WIDE-BANDWIDTH LOW-VOLTAGE PLL FOR POWERPC(TM) MICROPROCESSORS

被引:47
作者
ALVAREZ, J [1 ]
SANCHEZ, H [1 ]
GEROSA, G [1 ]
COUNTRYMAN, R [1 ]
机构
[1] MOTOROLA INC,SOMERSET DESIGN CTR,TECH STAFF,SEMICOND SECTOR,AUSTIN,TX 78758
关键词
D O I
10.1109/4.375957
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 mu m CMOS technology is described, The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC(TM) microprocessors. The CPU clock lock range spans from 6 to 175 MHz, Lock times below 15 mu s, PLL power dissipation below 10mW as well as phase error and jitter below +/-100 ps have been measured, The total area of the PLL is 0.52 mm(2).
引用
收藏
页码:383 / 391
页数:9
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