High-frequency pulse width modulation implementation using FPGA and CPLD ICs

被引:46
作者
Koutroulis, Eftichios [1 ]
Dollas, Apostolos [1 ]
Kalaitzakis, Kostas [1 ]
机构
[1] Tech Univ Crete, Dept Elect & Comp Engn, GR-73100 Khania, Greece
关键词
pulse width modulation; power converters; field programmable gate array; CPLD; counter;
D O I
10.1016/j.sysarc.2005.09.001
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Pulse width modulation (PWM) has been widely used in power converter control. Most high power level converters operate at switching frequencies up to 500 kHz, while operating frequencies in excess of 1 MHz at high power levels can be achieved using the planar transformer technology. The contribution of this paper is the development of a high-frequency PWM generator architecture for power converter control using FPGA and CPLD ICs. The resulting PWM frequency depends on the target FPGA or CPLD device speed grade and the duty cycle resolution requirements. The post-layout timing simulation results are presented, showing that PWM frequencies up to 3.985 MHz can be produced with a duty cycle resolution of 1.56%. Additionally, experimental results are also presented for low cost functional verification of the proposed architecture. (c) 2005 Elsevier B.V. All rights reserved.
引用
收藏
页码:332 / 344
页数:13
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