Jitter in ring oscillators

Jitter in ring oscillators is theoretically described, and predictions are experimentally verified, A design procedure is developed in the context of time domain measures of oscillator jitter in a phase-locked loop (PLL). A major contribution is the identification of a design figure of merit kappa, which is independent of the number of stages in the ring, This figure of merit is used to relate fundamental circuit-level noise sources (such as thermal and shot noise) to system-leveljitter performance. The procedure is applied to a ring oscillator composed of bipolar differential pair delay stages, The theoretical predictions are tested on 155 and 622 MHz clock-recovery PLL's which have been fabricated in a dielectrically isolated, complementary bipolar process. The measured closed-loop jitter is within 10% of the design procedure prediction.