Design, performance and status of the CLEO III silicon detector

被引:10
作者
Fast, J
Alam, MS
Alexander, J
Anastassov, A
Arndt, K
Bean, A
Bebek, C
Boyd, R
Brandenburg, G
Cherwinka, J
Darling, C
Duboscq, J
Gan, KK
Gao, Y
Hopman, P
Kagan, H
Kass, R
Kim, D
Lee, J
Menon, N
Miller, D
Oliver, J
Rush, C
Severini, H
Shipsey, I
Skubic, P
Spencer, M
Timm, S
Tourne, E
Ward, C
Zoeller, M
机构
[1] Purdue Univ, W Lafayette, IN 47907 USA
[2] SUNY Albany, Albany, NY 12222 USA
[3] Cornell Univ, Ithaca, NY 14853 USA
[4] Ohio State Univ, Columbus, OH 43210 USA
[5] Univ Kansas, Lawrence, KS 66045 USA
[6] Univ Oklahoma, Norman, OK 73019 USA
[7] Harvard Univ, Cambridge, MA 02138 USA
基金
美国国家科学基金会;
关键词
CLEO; silicon; microstrip; vertex; detector;
D O I
10.1016/S0168-9002(99)00405-2
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
The CLEO III silicon detector is part of a general upgrade of the CLEO detector to allow for operation at a luminosity of 2 x 10(33) cm(-2) s(-1), which will be provided by the Cornell Electron-Positron Storage Ring (CESR) beginning in 1999. The silicon detector is a four-layer barrel design covering radii from 2.5 to 10.2 cm with 93% solid angle coverage. The silicon sensors are DC-coupled and double-sided with double-metal readout on the p-side. The n-type strips measure phi, with 50 mu m pitch while the p-type strips measure z, the coordinate along the beam axis, with 100 mu m pitch. The readout electronics are mounted on BeO hybrids attached to the conical support structure and connected to the silicon sensors via a thin kapton flex cable. The electronics consist of an R/C chip with bias resistors and decoupling capacitors, a low-noise preamp/shaper chip and a digitizer/sparsifier chip. Readout is done using VME-based sequencer boards. Production of all detector components is nearing completion and installation of the detector will take place in early 1999. (C) 1999 Elsevier Science B.V. All rights reserved.
引用
收藏
页码:9 / 15
页数:7
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