A fully parallel vector-quantization processor for real-time motion-picture compression

被引:50
作者
Nakada, A [1 ]
Shibata, T
Konda, M
Morimoto, T
Ohmi, T
机构
[1] Univ Tokyo, VLSI Design & Educ Ctr, Tokyo 113, Japan
[2] Univ Tokyo, Dept Informat & Commmun Engn, Tokyo 113, Japan
[3] Tohoku Univ, Grad Sch Engn, Dept Elect Engn, Sendai, Miyagi 98077, Japan
关键词
D O I
10.1109/4.766816
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A vector-quantization (VQ) processor system has been developed aiming at real-time compression of motion pictures using a 0.6-mu m triple-metal CMOS technology. The chip employs a fully parallel single-instruction, multiple data architecture having a two-stage pipeline. Each pipeline segment consists of 19 cycles, thus enabling the execution of a single VQ operation in only 19 clock cycles. As a result, it has become possible to encode a full-color picture of 640 x 480 pixels in less than 33 ms, i.e,, the real-time compression of moling pictures has become available. The chip is scalable up to eight-chip master-slave configuration in conducting fully parallel search for 2-K template vectors. The chip operates at 17 MHz with a power dissipation of 0.29 W under a power-supply voltage of 3.3 V.
引用
收藏
页码:822 / 830
页数:9
相关论文
共 14 条
[1]   A LOW-POWER CHIPSET FOR A PORTABLE MULTIMEDIA I/O TERMINAL [J].
CHANDRAKASAN, AP ;
BURSTEIN, A ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) :1415-1428
[2]   REAL-TIME VIDEO COMPRESSION USING DIFFERENTIAL VECTOR QUANTIZATION [J].
FOWLER, JE ;
ADKINS, KC ;
BIBYK, SB ;
AHALT, SC .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, 1995, 5 (01) :14-24
[3]  
GENTILE A, 1996, P DAT COMPR C
[4]  
Gersho A., 1992, VECTOR QUANTIZATION
[5]   A half-pel precision MPEG2 motion-estimation processor with concurrent three-vector search [J].
Ishihara, K ;
Masuda, S ;
Hattori, S ;
Nishikawa, H ;
Ajioka, Y ;
Yamada, T ;
Amishiro, H ;
Uramoto, S ;
Yoshimoto, M ;
Sumi, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1995, 30 (12) :1502-1509
[6]  
KOBAYASHI K, 1996, P 22 ESSCIRC SEPT, P184
[7]  
Kohonen T., 1995, SELF ORG MAPS
[8]   A 200-MHZ 13-MM(2) 2-D DCT MACROCELL USING SENSE-AMPLIFYING PIPELINE FLIP-FLOP SCHEME [J].
MATSUI, M ;
HARA, H ;
UETANI, Y ;
KIM, LS ;
NAGAMATSU, T ;
WATANABE, Y ;
MATSUDA, K ;
SAKURAI, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) :1482-1490
[9]  
MIZUNO M, 1997, ISSCC, P256
[10]   A VIDEO DSP WITH A MACROBLOCK-LEVEL-PIPELINE AND A SIMD TYPE VECTOR-PIPELINE ARCHITECTURE FOR MPEG2 CODEC [J].
TOYOKURA, M ;
KODAMA, H ;
MIYAGOSHI, E ;
OKAMOTO, K ;
GION, M ;
MINEMARU, T ;
OHTANI, A ;
ARAKI, T ;
TAKENO, H ;
AKIYAMA, T ;
WILSON, B ;
AONO, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (12) :1474-1481