An approach for multilevel logic optimization targeting low power

被引:11
作者
Iman, S
Pedram, M
机构
[1] Department of Electrical Engineering-Systems, University of Southern California, Los Angeles
关键词
D O I
10.1109/43.511569
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 [计算机科学与技术];
摘要
This paper shows that using don't cares computed for area optimization during local node minimization may result in an increase in the power consumption of other nodes in a Boolean network. It then presents techniques for computing a subset of observability and satisfiability don't care conditions that can be used freely to optimize the local function of nodes. The concept of minimal variable support is then used to optimize the local function of each node for minimum power using its power relevant don't care set, that is, to reimplement the local function using a modified support that has a lower switching activity. Empirical results on a set of benchmark circuits are presented and discussed.
引用
收藏
页码:889 / 901
页数:13
相关论文
共 24 条
[1]
Precomputation-based sequential logic optimization for low power [J].
Alidina, Mazhar ;
Monteiro, Jose ;
Devadas, Srinivas ;
Ghosh, Abhijit ;
Papaefthymiou, Marios .
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1994, 2 (04) :426-436
[2]
MULTILEVEL LOGIC SYNTHESIS [J].
BRAYTON, RK ;
HACHTEL, GD ;
SANGIOVANNIVINCENTELLI, AL .
PROCEEDINGS OF THE IEEE, 1990, 78 (02) :264-300
[3]
BRAYTON RK, 1984, LOGIC MINIMIZATION A
[4]
CERNY E, 1977, IEEE T COMPUT, V26, P745, DOI 10.1109/TC.1977.1674912
[5]
LOW-POWER CMOS DIGITAL DESIGN [J].
CHANDRAKASAN, AP ;
SHENG, S ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484
[6]
COUDERT O, 1989, P WORKSH AUT VER MET
[7]
DAMIANI M, 1990, P IEEE INT C COMP AI, P502
[8]
HALATSIS C, 1978, IEEE T COMPUT, V27, P1064, DOI 10.1109/TC.1978.1674997
[9]
MINI - HEURISTIC APPROACH FOR LOGIC MINIMIZATION [J].
HONG, SJ ;
CAIN, RG ;
OSTAPKO, DL .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1974, 18 (05) :443-458
[10]
IMAN S, 1994, IEEE IC CAD, P372