Process to fabricate high performance solid phase crystallized n-type and p-type thin film transistors on glass substrate

We have perfected a low thermal budget process (<600 degrees C) to fabricate high performance nand p type TFT's. They are elaborated in polycrystalline silicon on low cost glass substrates for Active Matrice Liquid Crystal Display (AMLCD) applications. Amorphous silicon layers are deposited by Low Pressure Chemical Vapor Deposition (LPCVD) and subsquently solid phase crystallized. The flexibility of LPCVD with the control of the in-situ doping makes changes possible in the process. Indeed, this deposition technique allows the improvement of the polysilicon active layer/doped polysilicon layer interface. Drain and source regions are in-situ doped using phosphine for n type and diborane for p type transistors. The gate insulator is an Atmospheric Pressure Chemical Vapor Deposited (APCVD) SiO2 layer. The process does not include any hydrogenation step. This process allows the production of high TFTs with high characteristics uniformity on the whole substrate surface. Both n and p type TFT give high quality electrical properties : a high field effect mobility (mu(FEn) = 100 cm(2)/Vs, mu(FEp) = 60 cm(2)/Vs) and a low subthreshold slope (for both n and p type S = 0.6 V/dec).